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toshiba thm72v2010ag/atg-60/70 toshiba america electronic components, inc . 1 2,097,152 words x 72 bit dynamic ram module description the thm72v2010ag/atg is a 2,097,152 words by 72 bits dynamic ram module which assembled 9 pcs of tc51v17800anj/ant on the printed circuit board. this module is optimized for application to the systems which are required high density and large capacity such as main memory of the computers and as image memory systems, and to the others which are requested compact size. features 2,097,152 words by 72 bits organization fast access time and cycle time single power supply of 3.3v 5% low power - 4,095mw max. operating - (thmxxxxxx-60) - 3,470mw max. operating - (thmxxxxxx-70) - 50.4mw max. standby read-modify-write, cas before ras refresh, ras -only refresh, hidden refresh, and fast page mode capability all inputs and outputs ttl compatible 2,048 refresh cycles/32ms package: 168pin gold contact thm72v2010ag-x soj type thm72v2010atg-x tsop type key parameters -60 -70 t rac ra s access time 60ns 70ns t aa column address access time 35ns 40ns t cac cas access time 20ns 25ns t rc cycle time 110ns 130ns t pc fast page mode cycle time 40ns 45ns preliminary note ?? high level (buffered) ?? low level (buffered) -60 -70 pd0 ? ? pd1 ? l pd2 ? l pd3 ? ? pd4 ? l pd5 ? ? pd6 ? ? pd7 ? l id0 v ss v ss id1 v ss v ss 1. this technical data may be controlled under u.s. export administration regulations and may be subject to the approval of the u.s. department of commerce prior to export. any export or re-export, directly or indi- rectly, in contravention of the u.s. export administration regulations is strictly prohibited. 2. life support policy toshiba products described in this document are not authorized for use as critical components in life support systems without the written consent of the appropriate of?er of toshiba america, inc. life support sys- tems are either systems intended for surgical implant in the body or systems which sustain life. a critical component in any component of a life support system whose failure to perform may cause a malfunction of the life support system, or may affect its safety or effectiveness. 3. the information in this document has been carefully checked and is believed to be reliable; however no responsibility can be assumed for inaccuracies that may not have been caught. all information in this data book is subject to change without prior notice. furthermore, toshiba cannot assume responsibility for the use of any license under the patent rights of toshiba or any third parties.
thm72v2010ag/atg-60/70 standard dram dm16050295 2 toshiba america electronic components, inc . preliminary pin name pin connection (top view) b0, a0 ~ 9, a10r address inputs dq0 ~ 71 data input/outputs ras 0, 2 row address strobe cas 0, 4 column address strobe we 0, 2 write enable oe 0, 2 output enable v cc power (+3.3v) v ss ground pd0 ~ 7 presence detect pin id0, 1 id bit nc no connection 1v ss 85 v ss 18 v cc 102 v cc 35 a4 119 a5 52 dq18 136 dq54 69 dq28 153 dq64 2 dq0 86 dq36 19 dq14 103 dq50 36 a6 120 a7 53 dq19 137 dq55 70 dq29 154 dq65 3 dq1 87 dq37 20 dq15 104 dq51 37 a8 121 a9 54 v ss 138 v ss 71 dq30 155 dq66 4 dq2 88 dq38 21 dq16 105 dq52 38 a10r 122 nc 55 dq20 139 dq56 72 dq31 156 dq67 5 dq3 89 dq39 22 dq17 106 dq53 39 nc 123 nc 56 dq21 140 dq57 73 v cc 157 v cc 6v cc 90 v cc 23 v ss 107 v ss 40 v cc 124 v cc 57 dq22 141 dq58 74 dq32 158 dq68 7 dq4 91 dq40 24 nc 108 nc 41 nc 125 nc 58 dq23 142 dq59 75 dq33 159 dq69 8 dq5 92 dq41 25 nc 109 nc 42 nc 126 b0 59 v cc 143 v cc 76 dq34 160 dq70 9 dq6 93 dq42 26 v cc 110 v cc 43 v ss 127 v ss 60 dq24 144 dq60 77 dq35 161 dq71 10 dq7 94 dq43 27 we 0 111 nc 44 oe 2 128 nc 61 nc 145 nc 78 v ss 162 v ss 11 dq8 95 dq44 28 cas 0 112 nc 45 ras 2 129 nc 62 nc 146 nc 79 pd0 163 pd1 12 v ss 96 v ss 29 nc 113 nc 46 cas 4 130 nc 63 nc 147 nc 80 pd2 164 pd3 13 dq9 97 dq45 30 ras 0 114 nc 47 nc 131 nc 64 nc 148 nc 81 pd4 165 pd5 14 dq10 98 dq46 31 oe 0 115 nc 48 we 2 132 pde 65 dq25 149 dq61 82 pd6 166 pd7 15 dq11 99 dq47 32 v ss 116 v ss 49 v cc 133 v cc 66 dq26 150 dq62 83 id0 167 id1 16 dq12 100 dq48 33 a0 117 a1 50 nc 134 nc 67 dq27 151 dq63 84 v cc 168 v cc 17 dq13 101 dq49 34 a2 118 a3 51 nc 135 nc 68 v ss 152 v ss
dm16050295 standard dram thm72v2010ag/atg-60/70 toshiba america electronic components, inc . 3 preliminary block diagram
thm72v2010ag/atg-60/70 standard dram dm16050295 4 toshiba america electronic components, inc . preliminary absolute maximum ratings recommended dc operating conditions (ta = 0 ~ 70 c) *v cc + 1.2v at pulse width 20ns (pulse width is measured at v cc ). **-1.2v at pulse width 20ns (pulse width is measured at v ss ). symbol item rating unit note v in input voltage -0.3 ~ v cc + 0.3 v 1 v out output voltage -0.3 ~ v cc + 0.3 v 1 v cc power supply voltage -0.5 ~ 4.6 v 1 t opr operating temperature 0 ~ 70 c 1 t stg storage temperature -55 ~ 125 c1 p d power dissipation 3.9 w 1 i out short circuit output current 50 ma 1 symbol parameter min typ max unit note v cc supply voltage 3.13 3.3 3.47 v 2 v ih input high voltage 2.2 - v cc + 0.3* v 2 v il input low voltage -0.3** - 0.8 v 2
dm16050295 standard dram thm72v2010ag/atg-60/70 toshiba america electronic components, inc . 5 preliminary dc electrical characteristics (v cc = 3.3v 5%, ta = 0 ~ 70 c) capacitance (v cc = 3.3v 5%, f = 1mhz, ta = 0 ~ 70 c) symbol parameter min max unit note | cc1 operating current average power supply operating current (ras , cs , address cycling: t rc =t rc min.) thmxxxxxx-60 - 1180 ma 3, 4 5 thmxxxxxx-70 - 1000 | cc2 standby current power supply standby current (ras =cas =v ih ) -19ma | cc3 ras only refresh current average power supply current, ras only mode (ras cycling, cas =v ih : t rc =t rc min.) thmxxxxxx-60 - 1180 ma 3 , 5 thmxxxxxx-70 - 1000 | cc4 fast page mode current average power supply current, fast page mode (ras =v il , cas , address cycling: t pc =t pc min.) thmxxxxxx-60 - 685 ma 3, 4 5 thmxxxxxx-70 - 595 | cc5 standby current power supply standby current (ras =cas =v cc -0.2v) - 14.5 ma | cc6 cas before ras refresh current average power supply current, cas before ras mode (ras , cas cycling: t rc =t rc min.) thmxxxxxx-60 - 1180 ma 3 , 5 thmxxxxxx-70 - 1000 | i (l) input leakage current input leakage current, any input (0v v in v cc , all other pins not under test=0v) -10 10 m a | o (l) output leakage current (d out is disabled, (0v v out v cc ) -10 10 m a v oh output level output ? level voltage (i out = -2ma) 2.4 - v v ol output level output ? level voltage (i out =2ma) - 0.4 v symbol parameter min max unit c i1 input capacitance (b0, a0 ~ a9, a10r) - 13 p f c i2 input capacitance (we 0, 2) - 10 c i3 input capacitance (ras 0, 2) - 33 c i4 input capacitance (cas 0, 4) - 10 c i5 input capacitance (oe 0, 2) - 10 c i6 input capacitance (pde )-13 c dq i/o capacitance (dq0 ~ 71) - 30
thm72v2010ag/atg-60/70 standard dram dm16050295 6 toshiba america electronic components, inc . preliminary electrical characteristics and recommended ac operating conditions (v cc = 3.3v 5%, ta = 0 ~ 70 c) (notes 6,7,8) symbol parameter thmxxxxxx-60 thmxxxxxx-70 unit notes min max min max t rc random read or write cycle time 110 - 130 - ns t rmw read-modify-write cycle time 165 - 190 - ns t pc fast page mode cycle time 40 - 45 - ns t prmw fast page mode read-modify-write cycle time 95 - 105 - ns t rac access time from ras -60-70ns 9, 14, 15 t cac access time from cas -20-25ns9, 14 t aa access time from column address - 35 - 40 ns 9, 15 t cpa access time from cas precharge - 40 - 45 - 9 t clz cas to output in low-z 0-0- ns9 t off output buffer turn-off delay 0 20 0 20 ns 10 t t transition time (rise and fall) 3 50 3 50 ns 8 t rp ras precharge time 40 - 50 - ns t ras ras pulse width 60 10,000 70 10,000 ns t rasp ras pulse width (fast page mode) 60 200,000 70 200,000 ns t rsh ras hold time 20 - 25 - ns t rhcp ras hold time from cas precharge (fast page mode) 40-45- ns t csh cas hold time 60 - 70 - ns t cas cas pulse width 15 10,000 20 10,000 ns t rcd ras to cas delay time 20 40 20 45 ns 14 t rad ras to column address delay time 15 25 15 30 ns 15 t crp cas to ras precharge time 10 - 10 - ns t cp cas precharge time 10 - 10 - ns t asr row address set-up time 0-0- ns t rah row address hold time 10 - 10 - ns t asc column address set-up time 0-0- ns t cah column address hold time 10 - 15 - ns t ral column address to ras lead time 35 - 40 - ns t rcs read command set-up time 0-0- ns t rch read command hold time 0-0- ns11 t rrh read command hold time referenced to ras 10-10- ns11 t wch write command hold time 10 - 15 - ns
dm16050295 standard dram thm72v2010ag/atg-60/70 toshiba america electronic components, inc . 7 preliminary electrical characteristics and recommended ac operating conditions (cont) symbol parameter thmxxxxxx-60 thmxxxxxx-70 unit notes min max min max t wp write command pulse width 10 - 15 - ns t rwl write command to ras lead time 20 - 25 - ns t cwl write command to cas lead time 15 - 20 - ns t ds data set-up time 0-0-ns12 t dh data hold time 15 - 20 - ns 12 t ref refresh period - 32 - 32 ms t wcs write command set-up time 0-0-ns13 t cwd cas to we delay time 50 - 55 - ns 13 t rwd ras to we delay time 90 - 100 - ns 13 t awd column address to we delay time 65 - 70 - ns 13 t cpwd cas precharge to we delay time 70 - 75 - ns 13 t csr cas set-up time (cas before ras cycle) 10-10- ns t chr cas hold time (cas before ras cycle) 10-15- ns t rpc ras to cas precharge time 5-5-ns t cpt cas precharge time (cas before ras counter test cycle) 20-30- ns t roh ras hold time referenced to oe 15-15- ns t oea oe access time - 20 - 25 ns t oed oe to data delay 20 - 20 - ns t olz oe to output in low-z 0-0-ns t oez output buffer turn off delay time from oe 020020ns 10 t oeh oe command hold time 15 - 15 - ns t ods output disable set-up time 0-0-ns t wts write command set-up time (test mode in) 15 - 15 - ns t wth write command hold time (test mode in) 10 - 10 - ns t wrp we to ras precharge time (cas before ras cycle) 15 - 15 - ns t wrh we to ras hold time (cas before ras cycle) 10 - 10 - ns t pd pde to presence detect data in low-z - 10 - 10 ns t pdoff presence detect data turn off delay time from pde 1-1-ns
thm72v2010ag/atg-60/70 standard dram dm16050295 8 toshiba america electronic components, inc . preliminary electrical characteristics and recommended ac operating conditions (v cc = 3.3v 5%, ta = 0 ~ 70 c) (notes 6,7,8) symbol parameter thmxxxxxx-60 thmxxxxxx-70 unit notes min max min max ns t rc random read or write cycle time 115 - 135 - ns t pc fast page mode cycle time 45 - 50 - ns t rac access time from ras - 65 - 75 ns 9, 14, 15 t cac access time from cas -25-30ns9, 14 t aa access time from column address - 40 - 45 ns 9, 15 t cpa access time from cas precharge - 45 - 50 ns 9 t ras ras pulse width 65 10,000 75 10,000 ns t rasp ras pulse width (fast page mode) 65 200,000 75 200,000 ns t rsh ras hold time 25 - 30 - ns t csh cas hold time 65 - 75 - ns t rhcp cas precharge to ras hold 45 - 50 - ns t cas cas pulse width 20 10,000 25 10,000 ns t ral column address to ras lead 40 - 45 - ns
dm16050295 standard dram thm72v2010ag/atg-60/70 toshiba america electronic components, inc . 9 preliminary notes: 1. stresses greater than those listed under ?bsolute maximum ratings?may cause permanent damage to the device. 2. all voltages are referenced to v ss . 3. i cc1 , i cc3 , i cc4 , i cc6 depend on cycle rate. 4. i cc1 , i cc4 depend on output loading. speci?d values are obtained with the output open. 5. address can be changed one or less while ras =v il . in case of i cc4 , it can be changed once or less during a fast page mode cycle (t pc ). 6. an initial pause of 500 m s is required after power-up followed by 8 ras only refresh cycles before proper device operation is achieved. when the internal refresh counter is used, a minimum of 8 cas before ras refresh cycles instead of 8 ras only refresh cycles are required. 7. ac measurements assume t t =5ns. 8. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 9. this parameter is measured with a load equivalent to 100pf and at v oh =2.0v (i out = -2ma), v ol =2.0v (i out =2ma). 10. t off (max.) and t oez (max.) de?e the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 11. either t rch or t rrh must be satis?d for a read cycle. 12. these parameters are referenced to cas leading edge in early write cycles and to we leading edge in read-modify-write cycles. 13. t wcs , t rwd , t cwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) through the entire cycle; if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.), t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.) (fast page mode), the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell: if neither of the above sets of conditions are satis?d, the condition of the data out (at access time) is indeterminate. 14. operation within the t rcd (max.) limit insures that t rac can be met. t rcd (max.) is speci?d as a reference point only: if t rcd is greater than the speci?d t rcd (max.) limit, then access time is controlled by t cac . 15. operation within the t rad (max.) limit insures that t rac (max.) can be met. t rad (max.) is speci?d as a reference point only: if t rad is greater than the speci?d t rad (max.) limit, then access time is controlled by t aa .27
thm72v2010ag/atg-60/70 standard dram dm16050295 10 toshiba america electronic components, inc . preliminary timing waveforms read cycle
dm16050295 standard dram thm72v2010ag/atg-60/70 toshiba america electronic components, inc . 11 preliminary write cycle (early write)
thm72v2010ag/atg-60/70 standard dram dm16050295 12 toshiba america electronic components, inc . preliminary write cycle (oe controlled write)
dm16050295 standard dram thm72v2010ag/atg-60/70 toshiba america electronic components, inc . 13 preliminary read-modify-write cycle
thm72v2010ag/atg-60/70 standard dram dm16050295 14 toshiba america electronic components, inc . preliminary fast page mode read cycle
dm16050295 standard dram thm72v2010ag/atg-60/70 toshiba america electronic components, inc . 15 preliminary fast page mode write cycle (early write)
thm72v2010ag/atg-60/70 standard dram dm16050295 16 toshiba america electronic components, inc . preliminary fast page mode read-modify-write cycle
dm16050295 standard dram thm72v2010ag/atg-60/70 toshiba america electronic components, inc . 17 preliminary ras only refresh cycle cas before ras refresh cycle
thm72v2010ag/atg-60/70 standard dram dm16050295 18 toshiba america electronic components, inc . preliminary hidden refresh cycle (read)
dm16050295 standard dram thm72v2010ag/atg-60/70 toshiba america electronic components, inc . 19 preliminary hidden refresh cycle (write)
thm72v2010ag/atg-60/70 standard dram dm16050295 20 toshiba america electronic components, inc . preliminary cas before ras refresh counter test cycle
dm16050295 standard dram thm72v2010ag/atg-60/70 toshiba america electronic components, inc . 21 preliminary we , cas before ras refresh cycle
thm72v2010ag/atg-60/70 standard dram dm16050295 22 toshiba america electronic components, inc . preliminary presence detect data read cycle
dm16050295 standard dram thm72v2010ag/atg-60/70 toshiba america electronic components, inc . 23 preliminary read cycle in the test mode
thm72v2010ag/atg-60/70 standard dram dm16050295 24 toshiba america electronic components, inc . preliminary write cycle (early write) in the test mode
dm16050295 standard dram thm72v2010ag/atg-60/70 toshiba america electronic components, inc . 25 preliminary fast page mode read cycle in the test mode
thm72v2010ag/atg-60/70 standard dram dm16050295 26 toshiba america electronic components, inc . preliminary fast page mode write cycle in the test mode
dm16050295 standard dram thm72v2010ag/atg-60/70 toshiba america electronic components, inc . 27 preliminary test mode the tc51v17800anj/ant is the ram organized as 2,097,152 words by 8 bits, it is internally organized as 1,048,576 words by 16 bits. in ?est mode? data are written into 16 sectors in parallel by using only i/o1. a9c is not used. if, upon reading, 16 bits are equal (all ?s or ?s), the i/o8 pin indicates a ?? if they were not equal, the i/o8 pin would indicate a ?? other i/o pins (i/o1 ~ 7) always indicate a ??a during test mode read cycle. figure 1 shows the block diagram of tc51v17800anj/ant. in ?est mode? the 2mx8 dram can be tested as if it were a 1mx16 dram. ?e , cas before ras refresh cycle puts the device into ?est mode? and ?as before ras refresh cycle?or ?as only refresh cycle?puts it back into ?ormal mode? in the test mode, ?e , cas before ras refresh cycle?performs the refresh oper- ation with the internal refresh address counter. the ?est mode?function reduces test times (1/2 in case of n test pattern).
thm72v2010ag/atg-60/70 standard dram dm16050295 28 toshiba america electronic components, inc . preliminary block diagram in the test mode
dm16050295 standard dram thm72v2010ag/atg-60/70 toshiba america electronic components, inc . 29 preliminary outline drawing thm72v2010ag unit in mm
thm72v2010ag/atg-60/70 standard dram dm16050295 30 toshiba america electronic components, inc . preliminary outline drawing thm72v2010atg unit in mm

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